The present invention relates to the field of semiconductor devices and their manufacture. More specifically, in one embodiment the invention provides bipolar devices having high breakdown voltages.
Bipolar devices such as those of the present invention are commonly combined with other devices such as a p-channel metal-oxide semiconductor (PMOS). In one embodiment, PMOS devices are fabricated along with n-channel metal-oxide semiconductors (NMOS) devices to produce complementary metal-oxide semiconductor (CMOS) devices. Bipolar and CMOS devices are fabricated together to produce "BiCMOS" devices. BiCMOS devices offer the advantages of the high packing density and low power consumption of CMOS devices, as well as the high speed of bipolar devices. One BiCMOS device and process for fabrication thereof is described in U.S. Pat. No. 4,764,480 (Vora), assigned to the assignee of the present invention and incorporated herein by reference for all purposes.
One form of a bipolar device is a lateral PNP bipolar device. A common use of such a bipolar lateral device is as a voltage clamping device in programmable logic array (PLA) circuits. Programmable logic array circuits are programmed by providing a reverse bias voltage sufficiently high to program a vertical fuse or lateral fuse in components of the circuitry. However, it is desired that the voltage clamping devices be left unaffected by the reverse bias voltage during programming. Thus, the voltage clamping devices in PLA circuits must withstand a collector-to-emitter reverse bias voltage which is sufficient to program vertical fuse or lateral fuse devices. For this reason, it would be advantageous for a bipolar lateral devices to have a BV.sub.ceo value greater than the reverse bias voltage used to program a PLA circuit.